1. Field of the Invention
The method of avoiding dicing chip-outs in integrated circuit die disclosed herein is directed to the design and manufacture of integrated circuit die. More specifically, but without limitation thereto, this method is directed to dicing silicon wafers to produce integrated circuit die.
2. Description of Related Art
A silicon wafer used in the manufacture of integrated circuit die typically includes temporary metal structures such as probe contact pads that are constructed in the unused space between the die and are used to perform a functional test of the die on the wafer before dicing. The space between a row or column of die on the wafer is called a saw street. After wafer testing, the wafer is sawed apart by a dicing saw that runs over the saw street. The dicing saw divides the wafer into individual die, removing the temporary metal structures.